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Eight Character 5 mm Smart Alphanumeric Display Technical Data
HDSP-253x Series
Features
* XY Stackable * 128 Character ASCII Decoder * Programmable Functions * 16 User Definable Characters * Multi-Level Dimming and Blanking * TTL Compatible CMOS IC * Wave Solderable
Description
The HDSP-253x is ideal for applications where displaying eight or more characters of dot matrix information in an aesthetically pleasing manner is required. These devices are eightdigit, 5 x 7 dot matrix, alphanumeric displays. The 5.0 mm (0.2 inch) high characters are packaged in a 0.300 inch (7.62 mm) 30 pin DIP. The on-board CMOS IC has the ability to decode 128 ASCII characters, which are permanently stored in ROM. In addition, 16 programmable symbols may be stored in onboard RAM. Seven brightness levels provide versatility in
Applications
Avionics Computer Peripherals Industrial Instrumentation Medical Equipment Portable Data Entry Devices * Telecommunications * Test Equipment * * * * *
adjusting the display intensity and power consumption. The HDSP-253x is designed for standard microprocessor interface techniques. The display and special features are accessed through a bidirectional eight-bit data bus.
Device Selection Guide
AlGaAs Red HDSP-2534 HER Orange Yellow Green HDSP-2533 HDSP-2532 HDSP-2530 HDSP-2531
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Package Dimensions
PIN FUNCTION ASSIGNMENT TABLE PIN # FUNCTION PIN # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
0.25 (0.010)
FUNCTION GND (SUPPLY) THERMAL TEST GND (LOGIC) RD D0 D1 NO PIN NO PIN NO PIN D2 D3 D4 D5 D6 D7
42.93 (1.690) MAX.
1 RST FL 2PIN FUN 3PIN # FU A0 4 A1 1 R 5 A2 2 F 6 3 A3A A 7 4 NO PIN 5 A 8 6 NO PIN A
2.68 (0.105) SYM. 5.36 (0.211) TYP.
4.57 TYP. (0.180)
0
1
2
3
4
5
6
7
11.43 (0.450) MAX. 2.29 SYM. 0.090
2.54 (0.100) TYP. PIN # 1 IDENTIFIER DATE CODE (YEAR, WEEK) LUMINOUS INTENSITY CATEGORY COLOR BIN (3) [4] HP HDSP-253X YYWW XZ 5.31 (0.209) 4.01 TYP (0.158) PIN # 1 5.08 SYM (0.200)
97 8 10 9 1110 11 12 12 1313 1414 15 15
N NO PIN N A4 N CLS A C CLK C WR W CEC V VDD
PART NUMBER
______
1.52 REF. (0.060)
PIN #15
PIN # 15 PIN # 15 3.81 SYM 3.81 SYM. (0.150) (0.150)
PIN # 16
2.54 0.13 TYP. (0.100 0.005) (TOL. NON ACCUM.)
10.16 (0.400)
0.46 0.13 TYP. (0.018 0.005)
7.62 (0.300)
7.62 (0.300)
NOTES: 1. DIMENSIONS ARE IN MM (INCHES). 2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS 0.25 MM (0.010 IN.). 3. FOR YELLOW AND GREEN DISPLAYS ONLY. 4. MARKING IS ON SIDE OPPOSITE PIN 1.
Absolute Maximum Ratings
Supply Voltage, VDD to Ground[1] .................................... -0.3 V to 7.0 V Operating Voltage, VDD to Ground[2] .............................................. 5.5 V Input Voltage, Any Pin to Ground ........................... -0.3 V to VDD +0.3 V Free Air Operating Temperature Range, TA[3 ] .............. -40C to + 85C Relative Humidity (Non-Condensing) .............................................. 85% Storage Temperature Range, TS ...................................... -55C to 100C Wave Solder Temperature 1.59 mm (0.063 in.) below Body .............................. 250C for 3 secs ESD Protection @ 1.5 k, 100 pF ................................. 4 kV (each pin)
Notes: 1. Maximum Voltage is with no LEDs illuminated. 2. 20 dots ON in all locations at full brightness. 3. See Thermal Considerations section for information about operation in high temperature ambients.
ESD WARNING: NORMAL CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO AVOID STATIC DISCHARGE.
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ASCII Character Set
D7 D6 D5 0 0 0 D4 D3 D2 D1 D0 0 COLUMN ROW 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8-F 16 U S E R D E F I N E D C H A R A C T E R S 1 X X X
BI T
S
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Optical Characteristics at 25C[1]
VDD = 5.0 V at Full Brightness Luminous Intensity Character Average (#) IV (mcd) LED Color AlGaAs Red High Eff. Red Orange Yellow Green Part Number HDSP-2534 HDSP-2532 HDSP-2530 HDSP-2531 HDSP-2533 Min. 5.1 2.5 2.5 2.5 2.5 Typ. 25 7.5 7.5 7.5 7.5 Peak Wavelength PEAK (nm) Typ. 645 635 600 583 568 Dominant Wavelength[2] d (nm) Typ. 637 626 602 585 574
Notes: 1. Refers to the initial case temperature of the device immediately prior to measurement. 2. Dominant wavelength, d, is derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color of the device.
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Recommended Operating Conditions
Parameter Supply Voltage Symbol VDD Minimum 4.5 Nominal 5.0 Maximum 5.5 Units V
Electrical Characteristics over Operating Temperature Range
4.5 < VDD < 5.5 unless otherwise specified
Parameter Input Leakage (Input without pull-up) Input Current (Input with pull-up) IDD Blank IDD 8 digits 12 dots/char[2,3,4] (AlGaAs) IDD 8 digits 20 dots/char[2,3,4] (AlGaAs) IDD 8 digits 12 dots/char[2,3,4] (all colors except AlGaAs) IDD 8 digits 20 dots/char[2,3,4] (all colors except AlGaAs) Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low D0-D7 Output Voltage Low CLK Thermal Resistance IC Junction-to-PIN Symbol II IIP IDD(BL) IDD(V) IDD(#) IDD(V) IDD(#) VIH VIL VOH VOL VOL RJ-PIN 16 2.0 GND -0.3 V 2.4 0.4 0.4 Min. -1.0 -30 -11 0.5 230 330 200 300 -18 3.0 295 410 255 370 25C 25C Typ.[1] Max.[1] Max. 1.0 0 4.0 390 480 330 430 VDD +0.3 V 0.8 V V V V C/W VDD = 4.5 V, IOH = -40 A VDD = 4.5 V, IOL = 1.6 mA VDD = 4.5 V, IOL = 40 A Measured at pin 17 Units A A mA mA mA mA mA V Test Conditions VIN = 0 to VDD, pins CLK, D0-D7, A0-A4 VIN = 0 to VDD, pins CLS, RST, WR, RD, CE, FL VIN = VDD "V" on in all 8 locations "#" on in all 8 locations "V" on in all 8 locations "#" on in all 8 locations
Notes: 1. VDD = 5.0 V. 2. See Thermal Considerations Section for information about operation in high temperature ambients. 3. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x IDD(#). 4. Maximum IDD occurs at -55C.
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AC Timing Characteristics over Temperature Range
VDD = 4.5 to 5.5 V unless otherwise specified. Reference Number 1 Symbol tACC Description Display Access Time Write Read Address Setup Time to Chip Enable Chip Enable Active Time[2, 3] Write Read Address Hold Time to Chip Enable Chip Enable Recovery Time Chip Enable Active Prior to Rising Edge of Write Read Chip Enable Hold Time to Rising Edge of Read/Write Signal[2, 3] Write Active Time Data Valid Prior to Rising Edge of Write Signal Data Write Hold Time Chip Enable Active Prior to Valid Data Read Active Prior to Valid Data Read Data Float Delay Reset Active Time
[4] [2, 3]
Min.[1] 210 230 10 140 160 20 60 140 160 0 100 50 20 160 75 10 300
Units
ns ns
2 3
tACS tCE
ns ns ns
4 5 6
tACH tCER tCES
ns ns ns ns ns ns ns ns ns
7 8 9 10 11 12 13
tCEH tW tWD tDH tR tRD tDF tRC
Notes: 1. Worst case values occur at an IC junction temperature of 125C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. 4. The display must not be accessed until after 3 clock pulses (110 s min. using the internal refresh clock) after the rising edge of the reset line.
Symbol FOSC FRF[5] FFL[6] tST[7]
Notes: 5. FRF = FOSC /224. 6. FFL = FOSC /28,672. 7. tST = 262,144/FOSC.
Description Oscillator Frequency Display Refresh Rate Character Flash Rate Self Test Cycle Time
25C Typical 57 256 2 4.6
Minimum[1] 28 128 1 9.2
Units kHz Hz Hz sec
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Write Cycle Timing Diagram
INPUT PULSE LEVELS: 0.6 V TO 2.4 V
Read Cycle Timing Diagram
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Electrical Description
Pin Function RESET (RST, pin 1) FLASH (FL, pin 2) ADDRESS INPUTS (A0-A4, pins 3-6, 10) Description Reset initializes the display. FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A3-A4. Each location in memory has a distinct address. Address inputs (A0-A2) select a specific location in the Character RAM, the Flash RAM or a particular row in the UDC (User-Defined Character) RAM. A3-A4 are used to select which section of memory is accessed. Table 1 shows the logic levels needed to access each section of memory. Table 1. Logic Levels to Access Memory FL 0 1 1 1 1 CLOCK SELECT (CLS, pin 11) CLOCK INPUT/OUTPUT (CLK, pin 12) WRITE (WR, pin 13) CHIP ENABLE (CE, pin 14) READ (RD, pin 19) DATA Bus (D0-D7, pins 20, 21, 25-30) GND (SUPPLY) (pin 16) GND (LOGIC) (pin 18) VDD (POWER) (pin 15) Thermal Test (pin 17) A4 X 0 0 1 1 A3 X 0 1 0 1 Section of Memory Flash RAM UDC Address Register UDC RAM Control Word Register Character RAM A2 A1 A0 Character Address Don't Care Row Address Don't Care Character Address
This input is used to select either an internal (CLS = 1) or external (CLS = 0) clock source. Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. Data is written into the display when the WR input is low and the CE input is low. This input must be at a logic low to read or write data to the display and must go high between each read and write cycle. Data is read from the display when the RD input is low and the CE input is low. The Data bus is used to read from or write to the display. This is the analog ground for the LED drivers. This is the digital ground for internal logic. This is the positive power supply input. This pin is used to measure the IC junction temperature. Do not connect.
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Figure 1. HDSP-253X Internal Block Diagram.
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Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP-253X display. The CMOS IC consists of an 8 byte Character RAM, an 8 bit
Flash RAM, a 128 character ASCII decoder, a 16 character UDC RAM, a UDC Address Register, a Control Word Register and the refresh circuitry necessary to synchronize the decoding and
driving of eight 5 x 7 dot matrix characters. The major user accessible portions of the display are listed below:
Character RAM Flash RAM User-Defined Character RAM (UDC RAM) User-Defined Character Address Register (UDC Address Register) Control Word Register
This RAM stores either ASCII character data or a UDC RAM address. This is a 1 x 8 RAM which stores Flash data. This RAM stores the dot pattern for custom characters. This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. This register allows the user to adjust the display brightness, flash individual characters, blink, self test or clear the display.
Character Ram Figure 2 shows the logic levels needed to access the HDSP-253X Character RAM. During a normal access the CE = "0" and either RD = "0" or WR = "0". However, erroneous data may be written into the Character RAM if the Address lines are unstable when CE = "0" regardless of the logic levels of the RD or WR lines. Address lines A0-A2 are used to select the location in the Character RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D7 is used to differentiate between the ASCII character and a UDC RAM address. D7 = 0 enables the ASCII decoder and D7 = 1 enables the UDC RAM. D0-D6 are used to input ASCII data and D0-D3 are used to input a UDC address.
Figure 2. Logic Levels to Access the Character RAM.
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UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address Register. The UDC Address Register is eight bits wide. The lower four bits (D0-D3) are used to select one of the 16 UDC locations. The upper four bits (D4-D7) are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed. To completely specify a 5 x 7 character requires eight write cycles. One cycle is used to store the UDC RAM address in the UDC Address Register. Seven cycles are used to store dot data in the UDC RAM. Data is entered by rows. One cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an "F." A0-A2 are used to select the row to be accessed and D0-D4 are used to transmit the row dot data. The upper three bits (D5-D7) are ignored. D0 (least significant bit) corresponds to the right most column of the 5 x 7 matrix and D4 (most significant bit) corresponds to the left most column of the 5 x 7 matrix. Flash RAM Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input is used to select the Flash RAM. Address lines A3-A4 are ignored. Address lines A0-A2 are used to select the location in the Flash RAM to store the attribute. D0 is used to store or remove the flash attribute. D0 = "1" stores the attribute and D0 = "0" removes the attribute.
Figure 3. Logic Levels to Access a UDC Character.
Figure 4. Data to Load ""F'' into the UDC RAM.
When the attribute is enabled through bit 3 of the Control Word and a "1" is stored in the Flash RAM, the corresponding character will flash at approxi-
mately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock the flash rate can be calculated by dividing the clock frequency by 28,672.
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Figure 5. Logic Levels to Access the Flash RAM.
Control Word Register
Figure 6 shows how to access the Control Word Register. This is an eight bit register which performs five functions. They are Brightness control, Flash RAM control, Blinking, Self Test and Clear. Each function is independent of the others. However, all bits are updated during each Control Word write cycle. Brightness (Bits 0-2) Bits 0-2 of the Control Word adjust the brightness of the display. Bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0-2 also vary the average value of IDD. IDD can be calculated at any brightness level by multiplying the percent brightness level by the value of IDD at the 100% brightness level. These values of IDD are shown in Table 2. Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a "1," the output of the Flash RAM is checked. If the content of a location in the Flash RAM is a "1," the associated digit will flash at
Figure 6. Logic Levels to Access the Control Word Register
Table 2. Current Requirements at Different Brightness Levels for All Colors Except AlGaAs Symbol IDD (V) D2 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 % Brightness 100 80 53 40 27 20 13 VDD = 5.0 V 25C Typ. 200 160 106 80 54 40 26 Units mA mA mA mA mA mA mA
approximately 2 Hz. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. If the flash enable bit of the Control Word is a "0," the content of the Flash RAM is ignored. To use this function with multiple display systems see the Reset section. Blink Function (Bit 4) Bit 4 of the Control Word is used to synchronize blinking of all
eight digits of the display. When this bit is a "1" all eight digits of the display will blink at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems see the Reset section.
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Self Test Function (Bits 5, 6) Bit 6 of the Control Word Register is used to initiate the self test function. Results of the internal self test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = "1" indicates a passed self test and bit 5 = "0" indicates a failed self test. Setting bit 6 to a logic 1 will start the self test function. The built-in self test function of the IC consists of two internal routines which exercises major portions of the IC and illuminates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to "1." The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 KHz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self test function, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except for bit 5, and the Flash RAM is cleared and the UDC Address Register is set to all ones.
Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a "1" will start the clear function. Three clock cycles (110 s min. using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been completed, bit 7 will be reset to a "0." The ASCII character code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with "1"s. The UDC RAM, UDC Address Register and the remainder of the Control Word are unaffected.
blank the display. The Flash RAM and Control Word Register are loaded with all "0"s. The UDC RAM and UDC Address Register are unaffected. All displays which operate with the same clock source must be simultaneously reset to synchronize the Flashing and Blinking functions.
Mechanical Considerations
The HDSP-253X is assembled by die attaching and wire bonding 280 LED chips and a CMOS IC to a thermally conductive printed circuit board. A polycarbonate lens placed over the pcb creates an air gap over the LED wire bonds. A backfill epoxy seals the display package. Figure 8 shows the proper method to insert the display by hand. To prevent damage to the LED wire bonds, apply pressure uniformly with fingers located at both ends of the part. Using a tool, shown in Figure 9, such as a screwdriver or pliers to push the display into the printed circuit board or socket may damage the LED wire bonds. The force exerted by a screwdriver is sufficient to push the lens into the LED wire bonds. The bent wire bonds cause shorts or opens that result in catastrophic failure of the LEDs.
Display Reset
Figure 7 shows the logic levels needed to reset the display. The display should be reset on Powerup. The external Reset clears the Character RAM, Flash RAM, Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 s min. using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Character code for a space (20H) will be loaded into the Character RAM to
Figure 7. Logic Levels to Reset the Display.
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taneously at full brightness for 10 seconds at 25C as a lamp test. The IC has a maximum allowable junction temperature of 150C. The IC junction temperature can be calculated with the following equation: TJMAX = TA + (PD x RJ-A) TJMAX is the maximum allowable IC junction temperature. TA is the ambient temperature surrounding the display. PD is the power dissipated by the IC. RJ-A is the thermal resistance from the IC through the display package and printed circuit board to the ambient. A typical value for RJ-A is 39C/W. This value is typical for a display mounted in a socket and covered with a plastic filter. The socket is soldered to a 0.062 in. thick printed circuit board with 0.020 in. wide one-ounce copper traces. PD can be calculated as follows: PD = VDD x IDD VDD is the supply voltage and IDD is the supply current. VDD can vary from 4.5 V to 5.5 V. IDD changes with VDD, temperature, brightness level, and number of on-pixels.
Figure 9. Improper Method to Manually Insert a Display.
Figure 8. Proper Method to Manually Insert a Display.
Thermal Considerations
The HDSP-253X can operate from -40C to +85C. The display's low thermal resistance allows heat to flow from the CMOS IC to the 24 package pins. Typically, this heat is conducted through the printed
circuit board traces to free air. For most applications, no additional heatsinking is needed. Illuminating all 280 LEDs simultaneously at full brightness is not recommended for continuous operation. However, all 280 LEDs can be illuminated simul-
For AlGaAs IDD (#) = (83.8 x VDD -0.35 x TJ) x B x N/8 IDD(V) = (63 x VDD -0.79 x TJ) x B x N/8 For the other colors IDD (#) = (75.4 x VDD -0.28 x TJ) x B x N/8
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IDD(V) = (54 x VDD -0.6 x TJ) x B x N/8 IDD (#) is the supply current using "#" as the displayed character. IDD(V) is the supply current using "V" as the displayed character. TJ is the IC junction temperature. B is the percent brightness level. N is the number of characters illuminated. Operation in high temperature ambients may require power derating or heatsinking. Figure 10 shows how to derate the power for an HDSP-253X. You can reduce the power by tighter supply voltage regulation or lowering the brightness level. Table 3 shows the calculated maximum allowable ambient temperature for several different sets of operating conditions. The
worst case alphanumeric characters (#,@,B) have 20 pixels. Displaying eight 20-pixel characters will not occur in normal operation. Thus, using eight 20-pixel characters to calculate power dissipation will over estimate the power and the IC junction temperature. The average number of pixels per character, supply voltage, brightness level, and number of characters are needed to calculate the power dissipated by the IC. The ambient temperature, power dissipated by the IC, and the thermal resistance are then used to calculate IC junction temperature. The typical alphanumeric character is 15 pixels. For conditions not listed in Table 3, you can calculate the power dissipated by the IC and use Figure 10 to determine the maximum ambient temperature.
Figure 10. Maximum Allowable Power Dissipation vs. Ambient Temperature. TJMAX = 150 C or 120C.
Table 3. Maximum Allowable Ambient Temperature for Various Operating Conditions AlGaAs Red Character # (20 dots) # (20 dots) # (20 dots) # (20 dots) # (20 dots) # (20 dots) # (20 dots) # (20 dots) V (12 dots) Number of Characters 8 8 8 7 6 8 8 8 8 Brightness Level 100% 100% 100% 100% 100% 80% 80% 53% 100% VDD V 5.5 5.25 5.0 5.5 5.5 5.5 5.25 5.5 5.5 IDD mA 408 387 366 357 306 327 310 216 228 PD W 2.2 2.0 1.8 2.0 1.7 1.8 1.6 1.2 1.3 RJ-A
C/W
39 39 39 39 39 39 39 39 39
TAMAX
C
64 72 80 72 84 80 85 85 85
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Table 3. Maximum Allowable Ambient Temperature for Various Operating Conditions (cont'd.) All Colors Except AlGaAs Red Character # (20 dots) # (20 dots) # (20 dots) # (20 dots) # (20 dots) # (20 dots) V (12 dots) Number of Characters 8 8 8 7 6 8 8 Brightness Level 100% 100% 100% 100% 100% 80% 100% VDD V 5.5 5.25 5.0 5.5 5.5 5.5 5.5 IDD mA 373 354 335 326 280 298 207 PD W 2.0 1.9 1.67 1.8 1.5 1.6 1.1 RJ-A
C/W
39 39 39 39 39 39 39
TAMAX
C
72 77 85 80 85 85 85
The actual IC temperature is easy to measure. Pin 17 is thermally and electrically connected to the IC substrate. The thermal resistance from pin 17 to the IC is 16C/W. The procedure to measure the IC junction temperature is as follows: 1. Measure VDD and IDD for the display. Measure VDD between pins 15 and 16. Measure the current entering pin 15. 2. Measure the temperature of pin 17 after 45 minutes. Use an electrically isolated thermal couple probe. 3. TJ(IC) = Tpin + VDD x IDD x 16C/W.
Ground Connections
Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the analog ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long interconnections between the display and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. The logic ground should be connected to the same ground potential as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground which can withstand the current induced by the switching LED drivers.
When separate ground connections are used, the analog ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltage below -0.3 V can cause all dots to be on. Voltage above +0.3 V can cause dimming and dot mismatch.
Solder and Post Solder Cleaning
Note: Freon vapors can cause the black paint to peel off the display. See Application Note 1027 for information on soldering and post solder cleaning.
Contrast Enhancement (Filtering)
See Application Note 1015 for information on contrast enhancement.
Intensity Bin Limits for HDSP-2534
Bin I J K L M Intensity Range (mcd) Min. Max. 5.12 9.01 7.68 13.52 11.52 20.28 17.27 30.42 25.91 45.63
Note: Test conditions as specified in Optical Characteristic table.
Intensity Bin Limits for HDSP-253x
Bin G H I J K Intensity Range (mcd) Min. Max. 2.50 4.00 3.41 6.01 5.12 9.01 7.68 13.52 11.52 20.28
Note: Test conditions as specified in Optical Characteristic table.
Color Bin Limits
Color Green Bin 1 2 3 4 3 4 5 6 7 Color Range (nm) Min. Max. 576.0 580.0 573.0 577.0 570.0 574.0 567.0 571.0 581.5 585.0 584.0 587.5 586.5 590.0 589.0 592.5 591.5 595.0
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For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152 (Domestic/International), or 0120-61-1280 (Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2004 Agilent Technologies, Inc. Obsoletes 5988-4160EN July 14, 2004 5988-4669EN
Yellow
Note: Test conditions as specified in Optical Characteristic table.

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